Presentation
Aggressor Aware Design for Better IRdrop Results
DescriptionThe move to advanced technodes has many benefits, but it has created a challenge that has been previously neglectable; the aggression of neighboring cells that are linked through the power grid – this link through the grid is known as cross-impedance. The complex grid structure that designed with pillars create cross-impedance that stretch beyond cells that share same track.
Traditionally the focus of IRdrop analyses was mainly 2 aspects: i) improving self-drop –optimizing the cell's resistive path from its power pins to the bumps. ii) handling simultaneous switching cells that share a power\ground track.
To improve turn-around-time and reduce IRdrop related ECO cycles, we can tackle the problem from its origin – we can leverage Ansys Redhawk-SC platform to gather and calculate the aggression impact radius for all the cells in the library. The gathered data can be transformed to custom placement rules that will maximize cell usage while reducing overall dynamic IRdrop.
At later mature design stages, we can utilize Ansys Redhawk-SC platform to combine aggressor cells in the design with their slack to a small and effective list of ECO's that will have most overall design IRdrop improvements while having minimal impact on timing due to slack margin.
Traditionally the focus of IRdrop analyses was mainly 2 aspects: i) improving self-drop –optimizing the cell's resistive path from its power pins to the bumps. ii) handling simultaneous switching cells that share a power\ground track.
To improve turn-around-time and reduce IRdrop related ECO cycles, we can tackle the problem from its origin – we can leverage Ansys Redhawk-SC platform to gather and calculate the aggression impact radius for all the cells in the library. The gathered data can be transformed to custom placement rules that will maximize cell usage while reducing overall dynamic IRdrop.
At later mature design stages, we can utilize Ansys Redhawk-SC platform to combine aggressor cells in the design with their slack to a small and effective list of ECO's that will have most overall design IRdrop improvements while having minimal impact on timing due to slack margin.
Event Type
Engineering Track Poster
TimeMonday, July 10th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V