Power Integrity analysis of 3D stacking Structure in CMOS Image Sensor Chip
DescriptionFor the CMOS image sensor chip, to maximize the photoelectric signal conversion rate, minimize the loss, and reserve more design area for more complex image processing algorithm logic , two chips stacking is the common structure. One of ASIC die is below as image processing logic. The other CIS die is stacking above as Backside Illuminate Sensor for the perception of photoelectric signal. These two dies using different processes, are connected by intermediate hybrid-bonding layers. It makes difficulty to analyze the IR voltage drop of the PG network running through CIS die above and ASIC die below.
With the application of Ansys Redhawk-SC , which has powerful mutli-physics field co-simulation solutions, it is able to investigate the coupling between two different dies and multi-physics such as electric, thermal , structures etc., so as to achieve a higher simulation precision and guide designers to optimize index of SI/PI/themal/reliability of structure from SoC to system.
Engineering Track Poster
TimeMonday, July 10th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall