An automated flow for High Performance Asynchronous Digital Controllers
DescriptionDigital asynchronous logic design is a technique used to reach high performance in digital controllers for some analog IPs. The asynchronous digital controller is usually a local IP put inside the analog IP to minimize delays, power consumptions, area and boost the whole system performance.

This flow generates RTL code, timing constraints and regioning scripts for submodules (input logic, handshake logic and output logic) of the asynchronous digital controller.
In particular, the regioning applied during the implementation phase is the key point to meet the timing requirements for these kind of applications.
Also, a specific Static Timing Analysis for asynchronous digital controllers has been defined to guarantee that the timing constraints are met.

The use of this flow allows designers to reduce design time through automation. The results have shown an improvement on timing performance around 5%-10% with respect to the results obtained without regioning constraints.

This approach has been successfully applied to a large number of designs, resulting in a significant reduction in design time and effort to meet the required performance.
Event Type
Front-End Design
TimeTuesday, July 11th1:30pm - 1:45pm PDT
Location2010, 2nd Floor
Front-End Design