Presentation
SPET: Transparent SRAM Allocation and Model Partitioning for Real-time DNN Tasks on Edge TPU
DescriptionDeep neural networks (DNNs) have recently been deployed in many real-time safety-critical embedded systems. To support DNN tasks in real-time, most previous studies focused on GPU or CPU. However, Edge TPU has not yet been studied for real-time guarantee. This paper presents real-time DNNs framework for Edge TPU environments that satisfy multiple DNN inference tasks' timing requirements. This framework provides 1) SRAM allocation and model partitioning techniques, and 2) MIP-based algorithm that determines amounts of SRAM and segment count for each task. The experiment result shows that our framework provides 37% higher schedulability than the existing Edge TPU system.
Event Type
Research Manuscript
TimeWednesday, July 12th4:25pm - 4:40pm PDT
Location3008, 3rd Floor
Embedded Systems
Time-Critical System Design